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Volume 1, Issue 17: Thursday, September 25, 2003

  • "Design Outsourcing Appears Inevitable, EEs Told"
    EE Design (09/24/03); Wilson, Ron

    An IC design outsourcing panel at this week's Custom Integrated Circuits Conference said the rising tide of offshore design outsourcing was a necessary shift for the global industry, but that U.S. engineers could save their jobs by moving to systems-level design and to specialized fields such as RF and analog. University of California Berkeley political science professor Ann Lee Saxenian said her research showed the United States with just 30 percent of the global semiconductor market in 2010, while the Asia-Pacific share would grow to 35 percent and Japan's would drop to 20 percent. Saxenian said globalization was the real culprit, and that the U.S. would retain preeminence only in fields where it held productivity advantages, such as architectural design, industry investment, and design of manufacturing and EDA tools. TSMC USA President Ed Ross said Taiwan and China were becoming design powerhouses, especially with Taiwanese managers migrating to the mainland, where an industry fueled by government subsidies and a strong local market could produce global overcapacity by 2005 or 2006. Wipro Technologies vice president Werner Goertz, however, said design outsourcing would bring greater overall profits to the U.S. semiconductor industry, which in turn would ensure U.S. engineering jobs in architectural design and design management. The 2005 estimate of outsourced design jobs, about 3 million positions, would be marginally more than design jobs lost in 1997 through regular operations, Goertz said. ChipWrights CEO Brian Fitzgerald disagreed, saying the economic imperative facing his company meant less compensation and incentive for his U.S. workers, which he predicted would eventually harm national innovation.
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  • "New Sun Chip May Unseat the Circuit Board"
    New York Times (09/22/03) P. C1; Markoff, John

    Sun Microsystems researchers have come up with a way for chips to communicate without a circuit board and accompanying wires. The closer, more numerous connections mean data transmission speeds 60 to 100 times faster than with conventional architecture. The Sun team, which includes modern computing pioneer and Sun vice president Ivan E. Sutherland, will present their experimental findings at the Custom Integrated Circuits Conference on Sept. 23. The technique places chips one atop the other with face-to-face transmitters and receivers just microns in width. By comparison, the pads used for circuit board solder connections are about 100 microns wide and require much more power to push the signal. Sun's research is part of a Defense Advanced Research Projects Agency program to develop a next-generation computing architecture, and could revive hopes for wafer-scale circuits that are much more efficient but difficult to produce compared to current piecemeal computer architectures. Many computing luminaries have made famously wasted efforts to commercialize wafer-scale integration, including University of California, Berkeley, computer scientist David Patterson, who is also currently a Sun consultant; Patterson worked on military research in the 1970s for Hughes Aircraft that aimed to produce wafer-scale chip conglomerations. He says not having to chop up circuits on the wafer and then solder them back together would allow for even smaller computer form factors. In the early 1980s, IBM 360 mainframe designer Gene M. Amdahl founded Trilogy Systems with the express purpose of creating mainframe systems with wafer-scale technology. Still, Sun's Sutherland admits the current effort could be stymied by formidable obstacles, including cooling and interference between transmitters and receivers.
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  • "Conference Focuses on Teamwork"
    Times Union (09/23/03); Aaron, Kenneth

    Semiconductor industry leaders this week gathered at the Albany Symposium, held in Albany, N.Y., to network and discuss the need for shared costs in cutting-edge research. The technical and economic hurdles facing semiconductor companies are driving increased partnership, said International Sematech chief executive Michael Polcari, whose consortium is quickly growing its research arm at the University of Albany. Semiconductor Industry Association President George Scalise said that research partnerships alone were not enough, but that U.S. governmental groups needed to heed New York's example and gather research together with actual manufacturing capabilities. International competition is heating up, especially in China, Scalise noted. Among the challenges facing semiconductor companies are decreasing sizes and the current leakage that accompanies them. IBM Microelectronics head John E. Kelly III said collaborative efforts such as Albany NanoTech would be able to address those types of giant problems. Kelly also noted that only three U.S. companies have announced plans to build next-generation fabrication plants capable of producing 300mm wafers: IBM, Intel, and Texas Instruments. The symposium was sponsored by Albany NanoTech and the Albany development group, the Center for Economic Growth.
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  • "AMD Explores Triple-gate Transistors"
    CNet (09/18/03); Kanellos, Michael

    Chip makers are rethinking the basic design conventions of their products since heat dissipation and electricity leakage make smaller chips problematic. Increasing chip speed without decreasing component size means using new materials, stretching the silicon lattice, using metal junction gates, and adding insulating layers to wafers. AMD announced its latest effort with tri-gate transistors that could go into production by 2007, according to AMD's Craig Sander at the International Conference on Solid State Devices and Materials. The tri-gate transistor will use a fully depleted silicon-on-insulator layer, completely eliminating electricity loss, and has nickel silicide gates that conduct more efficiently than silicon and also strain the silicon lattice as a beneficial by-product. Intel President Paul Otellini noted at the recent Intel Developer Forum that today's chips use nearly half the elements on the periodic table whereas 1980s-era chips used only about 15 elements. Microprocessor Report editor-in-chief Peter Glaskowsky adds that some of those new materials are even radioactive. Intel divulged its tri-gate transistor idea in June, and AMD has already proposed dual, fin-shaped transistors as an alternative. Intel's Prescott chip due out this year uses strained silicon to increase performance while IBM and AMD have taken to silicon on insulator first.
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  • "Engineers Win $10K"
    Cornell Daily Sun (09/18/03); Flynn, Peter

    A pair of Cornell University chip design teams fared well in the recent SiGe Design Challenge, which solicited a total of 59 design entries by college students. Silicon Germanium (SiGe) has been widely used in the cell phone industry, but has yet to reach its full potential in fiber-optic transceivers, radar systems, and other high-speed communications applications. SiGe devices run fast, but cost less and use less electricity than devices made from other high-speed materials. Moreover, SiGe allows tighter integration, which reduces overall device cost. A three-person Cornell team won a $10,000, third-place prize for a 10-Gbps fiber-optic transceiver that integrated a number of usually separate chip components. Graduate student Hong Conan Zhan said SiGe technology provided adequate high-speed performance at much less cost than other alternative materials. The other team, which placed among the final 15 designs that were fabricated by IBM, produced an integrated cell phone chip that scaled amplifier signal according to how far the unit was from the transmission tower. Cornell professor Kevin Kornegay says the two design wins show the rapid progress the school's Broadband Communications Research Lab has made in the three years since it was established.
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  • "The Best Papers From CICC"
    EE Times (09/19/03); Clendenin, Mike

    The 2003 Custom Integrated Circuits Conference in San Jose, Calif., this year samples all the contentious and emerging topics in the industry, ranging from process technology to innovative memory architectures to packaging challenges. Both Infineon Technologies and IBM Microelectronics will issue papers about dealing with smaller CMOS geometries. Infineon researchers tackle silicon modeling's affect on nonlinear signals, process variation, and mask imperfections. IBM addresses three-dimensional gates and gate leakage. Macronix International touts new nonvolatile, phase-change memory embedded on SoC devices with a special doping scheme to speed write and read times. Alcatel and Mentor Graphics study the implications of embedded software on SoCs, which they say must be considered early-on as with packaging. Motorola looks at the pros and cons associated with SoCs and systems-in-packages, while Qualcomm and the University of California, San Diego, present a paper studying the increasing design importance of RF ICs and packages.
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  • "Intel Maps Out Future Chip Architectures"
    Cyber India Online (09/17/03); Varma, Yograj

    Intel President Paul S. Otellini laid out the company's medium-term roadmap at this week's Intel Developer Forum. Otellini said chip designers needed to consider the rising importance of Chinese and Indian markets and wireless systems. Specifically, he predicted 2.5 billion wirelessly connected handheld devices with the processing power of today's PCs by 2010. Intel is working on advanced wireless standards such as WLAN for 802.11 that will improve both the range and bandwidth of those technologies, but said there would be no standards war since new adaptive spectrum technologies let devices choose the best connection. Electronics firms need to re-evaluate their product portfolio and tailor it to the needs of the Chinese and Indian markets, noting China is already No. 1 in landline, mobile phone, and cable TV markets. North American market share will decrease as the global market grows, he said. Intel's current technology initiatives are Hyper Threading, Centrino Mobile Technology, LaGrande security technology, and Vanderpool technology, which brings virtualization to the desktop. Further out, Otellini said Intel was on track to produce 22nm chips by 2010 and showed off a prototype silicon wafer built at 65nm.
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  • "Silicon Chip Mimics Function of Octopus Retina"
    Newswise (09/22/03)

    An analog chip that mimics the retina of an octopus could help autonomous robots work in space or underwater exploration, according to the chip's creator, University at Buffalo optical engineer Albert H. Titus. The chip distinguishes objects the same way an octopus does, using brightness, size, and orientation, though it also has some of the same drawbacks, including an inability to differentiate halves of horizontally mirrored objects, such as an image of the letter "X." The chip also lacks the ability to see polarized light, an important component in an octopus' underwater vision system. Eventually, Titus aims to create a complete underwater vision system, and says vision systems for other applications should replicate natural adaptations, such as those of an eagle for long-distance vision systems, and those of zebras or lions for desert environments. The octopus retina was an elegant solution that also was relatively easy to replicate, he adds. Another chip Titus designed mimics natural eyes' ability to compress data at the periphery of sight, called edge detection. This lets natural eyes quickly detect and track objects using only the most important information. Titus' optical systems work is funded by the National Science Foundation.
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  • "Nanowires Line Up for Plastic Electronics"
    nanotechweb.org (09/18/03); Kalaugher, Liz

    Researchers at Nanosys have created nanowire thin-film transistors with significantly better electrical performance than thin-film transistors made from amorphous silicon or polycyrstalline silicon. Nanosys scientist Xiangfeng Duan said the work takes nanomaterials in a new direction; exploiting them for use in conventional electronic fabrication instead of for electronic miniaturization. The p-type silicon nanowires, formed through chemical vapor deposition, were assembled through flow-directed alignment at room temperature, with interspacing between 500nm and 1,000nm. Conventional lithography and metalization defined source and drain electrodes. Duan said parallel single-crystal nanowires acted like continuous bridges for high-carrier mobility--much improved over other thin-film transistors. Nanosys chemistry director Chunming Niu said the research was also applied to plastic substrates and could potentially serve to integrate nanoelectronics, microelectronics, and macroelectronics, as well as pave the way for applications such as "smart textiles" and "electronic paper."
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  • "Voltage, Topology Challenges Await Analog"
    Electronic Engineering Times--Asia (09/16/03); Soenen, Eric

    Unlike digital components, analog circuits do not perform better at smaller geometries--namely 130nm and 90nm, writes Barcelona Design's Eric Soenen. Designers were able to deal with shrinking voltage ranges at smaller process nodes with clever circuit tricks, but analog circuits face unprecedented noise limitations at the low voltages required by digital core transistors at the 130nm and 90nm nodes. Some manufacturers have overcome this obstacle by employing I/O transistors with longer gate lengths, allowing for higher interconnect density and lower leakage without voltage limitations. With the 90nm process, this may involve new design rules and redesigning analog blocks for transistors, Soenen says.
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  • "Making Interconnects More Flexible"
    Electronics Times (UK) (09/10/03); Bees, Duncan; Holden, Brian

    The multiple types of system bus options available for telecom, storage networking, and datacom applications present a challenge to chip designers, who could find themselves having to support a variety of interfaces, particularly for devices that are used in all of these domains. Authors Duncan Bees and Brian Holden of PMC-Sierra look at ways to develop a flexible interconnect that is able to work with a variety of bus interfaces, and the specific interfaces they examine are PCI, PCI-X, PCI-Express (PCI-Ex), HyperTransport (HT), parallel RapidIO (RIO), and serial RapidIO. While PCI-X is essentially an extension of the older PCI, the other three types of interconnect in question are a new class that could be of interest to telecom and datacom vendors, offering flexibility, well layered logical structures, scalable bandwidth, and high-speed, pin-efficient differential I/O. The authors present a table showing the general characteristics of these five interconnects and buses, then show an interconnect block diagram that could be an end-point implementation of an interconnect combining PCI-Ex, HT, and RIO. In order to find the similarities between interfaces that can be exploited to create a flexible interface, designers should look at the following six characteristics: number of outstanding transactions, multiple priority support, multiple flows between given source-destination pairs, ordering models, coherency support, and data link layer properties. The authors examine issues involved with developing a flexible physical interface for serial and parallel interconnects, including electrical precursor, data scrambling, data and control character encoding, and link speeds for serial interconnects and electrical basis, DC common mode, transmitter signal swing, and single-ended signals for parallel interconnects.
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  • "Darpa to Fund Optical Interconnect Research"
    EE Times (09/11/03); Johnson, R. Colin

    Agilent Technologies and IBM have received a $30 million grant to develop high-speed optical interconnects that will allow tomorrow's super-chips to talk to one another. The aim is to develop a chip-sized optical module that will dramatically shorten electrical line runs and eliminate cabled, rack-to-rack frameworks. "We will increase per-channel speed, but probably our most aggressive goal is to reduce power to 5-to-10 milliwatts per gigabit," says IBM Research optical communications senior manager Marc Taubenblatt. Agilent communications and optics research director Waguih Ishak predicts terabit-bit-speeds in small form factors, enabled by innovative integration and packaging, and by increasing the operating speeds of miniature optical components. With modules containing many separate high-speed channels, the researchers expect to avoid the cost and power utilization of discrete components. Darpa sponsorship of the project dovetails with its High Productivity Computing Systems program, which seeks to build next-generation computer chips.
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  • "Study Reveals Why Silicon Crystals Lose Their 'Edge'"
    Ohio State Research News (09/15/03)

    Heating and then cooling silicon crystals causes their normally sharp edges to morph, and a recent study at Ohio State University (OSU) found the mechanism that causes that transformation could be used to manufacture semiconductor components just nanometers in size. OSU professor William F. Saam and graduate student Vivek B. Shenoy revisited an MIT experiment done in the mid 1990s that concluded that changes in silicon crystal surfaces when heated above 1000 Kelvin were due to reasons other than what Saam found. Saam and Shenoy derived equations that showed the surface change was due to phase transformation that normally occurs in even the most rigid of materials, such as cut diamonds, over long periods of time. By heating and cooling the silicon crystals, surface atoms rearranged themselves according to external or internal forces--forces Saam says could be manipulated to create specific silicon crystal structures. The MIT experiment, for example, left the silicon crystal surface replete with small, interlocking pyramids that could be used as a template for growing nanowires or for quantum dot wells. Saam hopes experimental physics teams test his findings.
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  • "SoC Heralds the Use of Mystery Technology"
    Electronics Weekly (UK) (09/10/03); Howarth, Roger

    The SPIRIT (Structure for Packaging, Integrating, and Re-using IP within Tool-flows) Consortium intends to issue new standards, based on schema technology, for managing IP in SoC designs by the end of the year. The effort was announced at the DAC 2003 meeting. As SoC designs become more complex, they require collaboration between teams of engineers with different expertise. Schema technology will allow IP to be systematically described and cataloged in a database so that users can view the criteria pertinent to their specific task. The standardized system will reduce costs, and facilitate reuse and integration of IP for increased flexibility and productivity. Another benefit is automated IP integration, writes Beach Solutions' Roger Howarth.
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  • "Three-in-Five Chip Designs First-time Wrong, Says Report"
    Silicon Strategies (09/10/03); Clarke, Peter

    The majority of first-time ASIC and integrated circuit designs must be redesigned and sent back to the fabrication plant for a "respin," according to a report on the DeepChip Web site that cites Synopsys' CEO Aart de Geus. DeepChip's Email Synopsys User Group (ESNUG) newsletter is independent of the company and organized by the site's editor, John Cooley. De Geus' remarks were taken from his keynote address at the Synopsys User Group meeting earlier this month and should correctly represent EDA industry productivity given the company's leading position. Functional logic errors are responsible for 43 percent of design failures, followed by analog "tuning" at 20 percent and signal integrity at 17 percent. Flaws that occur in at least 10 percent of first-time designs include clock schemes, reliability issues, mixed-signal problems, too much power, and paths either too fast or too slow.
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  • "Computing About to Take a Giant Step in Tiny World"
    Globe and Mail (09/18/03); Ticoll, David

    Molecular electronics will make the existing microprocessor industry obsolete, according to experts working on the concept. For the past several decades, computing has advanced in lock-step with Moore's Law, doubling transistor density every 18 months and thus doubling processing power. In 1997, Gordon Moore himself said two fundamental obstacles limited the continued feasibility of this paradigm, namely the increasing expense of mechanical precision in lithography and the fact that transistors cannot be made smaller than a single molecule. The effects of these pressures are already being seen in the rapidly rising cost of chip fabrication plants, which today cost approximately $3 billion but could cost as much as $50 billion in the future. Molecular electronics, however, eliminates the need for mechanical manipulation in the chip-making process and also promises computing components much smaller than what is available today. Hewlett-Packard senior researcher Philip Kuekes likens the process of creating molecular electronics to stewing soup, allowing chemical and physics laws to guide the self-assembly of nanowire grids and transistor junctions. Hewlett-Packard has already created a prototype 8x8 nanowire grid that can theoretically store 64 bits of data; the process involves growing parallel nanowires just nanometers apart, then spraying on special "rotaxane" molecules, and finally layering another set of nanowires crosswise to the first. Trapped molecules at the nanowire-grid intersections work as switches that can be manipulated by low voltage. Kuekes says the small size and low power requirements of the new computing components will change the way people think of computers: "It won't be on your wristwatch--it will be in the fiber of your shirt" and powered by ambient light, he predicts.
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  • "In PC Design, Harbingers of Shrink"
    CNet (09/16/03); Frauenheim, Ed; Kanellos, Michael

    Industry insiders predict a 2004 market debut for products built from several technologies designed to reduce the size of notebooks and desktops, and enable more malleable configurations of standard PCs. Such technologies include PCI Express, a new technique for linking together PCs and peripherals that could lead to shrinkage of machines' inner mechanics; ExpressCard, a PC expansion card standard that supporters claim will supplant PCMCIA cards used to boost memory or establish network connections; and the high-speed Serial ATA disk drive interface standard that can reduce the cabling inside PC boxes. The technologies all share a serial nature rather than depending on parallel data exchange typical of most computers. PCMCIA Chairman Brad Saunders reports that the PC expansion card's overhaul is being driven by the emergence of PCI Express. Saunders' organization says that it is simpler for PC manufacturers to adopt the ExpressCard than the current CardBus card, because the former requires just 26 pins to connect to a PC while the latter needs 68 pins. The ExpressCard standard, which was developed by Hewlett-Packard, IBM, Dell, Microsoft, Lexar Media, and others, comes in two sizes: The larger accommodates applications such as compact flash memory and 1.8-inch hard drives, while the smaller is supposed to have a long-term value as a tool for smaller PCs. Saunders thinks the ExpressCard standard will allow computer makers to try out new designs, while the PCMCIA indicates that desktops could be equipped with the new cards as well; this would enable users to expand their machines without dissecting them. PCI-SIG Chairman Tony Pierce says the PCI Express method could spawn new desktop architectures, one example being separate CPUs and graphics chips so heat can be more easily dissipated around the components.
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  • "Cooling Influence"
    Design Engineering (09/15/03); Excell, Jon

    A small vibrating membrane can create an air vortex powerful enough to cool electronic equipment, according to representatives from Innovative Fluidics, a spinoff company from the Georgia Institute of Technology. Innovative Fluidics' Jon Goldman could not name the membrane material because of patent status, but said research centered on loudspeakers and piezoelectrics. By inaudibly vibrating, the SynJet product mixes the air and importantly breaks up the layer immediately surrounding heatsink fins. Goldman described the unit as the size of a Ritz Cracker and said it would prove most useful in applications where traditional air-cooling was hard to implement. In laptop memory modules, for instance, engineers go to great lengths to position fan air-flow over modules, but with a SynJet underneath the modules, they could be placed almost anywhere. The flat shape and low flow rate also point toward applications in handheld devices. Goldman said the first prototype was one year away, but that Innovative Fluidics was talking with a number of companies about applications, including LCD projectors, lasers, and laptop batteries. Meanwhile, NEC announced a cooling module in development that would integrate a slim piezoelectric pump, water-cooled heatsink, and cooling fan. The system should be ready for commercial use in two years.
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  • "What Goes Around Comes Around"
    EDA Weekly (09/19/03); Aycinena, Peggy

    Vertical integration should be the new trend for the semiconductor industry as design nodes move below 0.13 micron, according to Kevin Meyer, vice president of worldwide marketing and sales at Chartered Semiconductor. Chartered recently announced the formation of the NanoAccess Alliance to support Chartered's NanoAccess semiconductor manufacturing technologies for 90 nanometers and below, as the company has been working on qualification of design libraries, memory components, EDA tool support, and third-party IP for the 90-nanometer mode since it announced its joint development agreement with IBM in November 2002. The NanoAccess Alliance currently includes ARM, Artisan Components, Cadence Design Systems, ChipIdea Microlectronics, IBM, Mentor Graphics, MoSys, QualCore Logic, Synopsys, and Virage Logic, as well as outsourced design and manufacturing services firms. Meyer says that a decade ago, "virtually every semiconductor company was an IDM in the sense that they did the design, had their own process technology development, and their own manufacturing capacity," but this all changed by 2000 as outsourcing relationships and value-added IP became more important. However, now that designs have moved lower than 0.13 micron, says Meyer, "Suddenly the ability to reaggregate IP has became very difficult, reversing the pendulum, and [triggering a situation where] companies that want to be successful have to design their processes to meet the application need, need to have a priori knowledge of the tools, the IP, and so forth." Thus, Chartered's announcements released in conjunction with IBM represent "the availability to customers of the deliverables required to do a 90-nanometer design, starting off with a very comprehensive design manual that includes the design rules needed to do 90 nanometers," Meyer says.
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  • "SystemC Draws Interest From Target Group"
    Electronic Design (09/15/03) Vol. 51, No. 20, P. 38; Maliniak, David

    Systems-on-a-chip (SoC) architects at systems houses are increasingly embracing the SystemC modeling platform and design language for high-level architectural exploration. "When we first launched SystemC, it might not have been clear that it wasn't meant to replace Verilog or the implementation flow in most semiconductor companies," says Kevin Kranen, president of the Open SystemC Initiative (OSCI). Although designers of bleeding-edge processors from Intel or nVidia have shown interest in SystemC, surveys do not show it to be highly rated as a hardware design language. Instead, users have adopted SystemC for software design, abstract algorithm modeling, software co-verification, design partitioning, and creation of "golden" modules of system functionality. A survey taken during the 3rd Japan SystemC User's Forum early in the year revealed that most attendees use SystemC for system-level modeling and testbench creation and verification. Meanwhile, a survey taken during the OSCI technology symposium at the Design Automation Conference found that half of respondents believe SystemC would benefit from automatic implementation.
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  • "Silicon Segmentation"
    EDN Magazine (09/18/03) Vol. 48, No. 20, P. 57; Dipert, Brian

    Designers have become accustomed to what are considered the usual tradeoffs between FPGAs and ASICs--for example, FPGAs are thought of as combining the advantage of flexibility and speed to market with the disadvantage of power-hungriness, while ASICs conversely are thought to combine efficient use of resources with complicated and costly development. A middle ground between these two has historically been the gate array, another category of ASIC that combines some of the advantages of both FPGA and standard-cell ASIC, but in recent years gate arrays have become less widely used. Now, some ASIC suppliers have used their expertise as gate-array suppliers to create a new type of product called the structured ASIC, also known as a modular array or structured array. Generally speaking, the structured ASIC is a gate-array derivative with a coarse-grained logic cell more like that of an FPGA, which means it requires less in the way of user-configurable metal and via layouts. Some of the companies now offering variations on this product category are AMI Semiconductor, Chip Express, Faraday Technology, Fujitsu, Lightspeed Semiconductor, NEC, and ViASIC. There are efforts going on among some of these companies to improve power usage by putting circuits into diffused portions of the chip, rather than using generic logic structures. Examples of this are the RapidChip line from LSI Logic and the RapidWorx tool set LSI is delivering in partnership with Synplicity and Tera Systems. Meanwhile, some competitors are less impressed with the claims of structured-ASIC vendors; for example, Actel and QuickLogic say their antifuse FPGAs offer similar density and performance with greater flexibility in design and manufacturing.
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  • "Integration at Last"
    Electronic Business (09/03) Vol. 29, No. 12, P. 28; James, Geoffrey

    EDA leaders Cadence and Synopsys are taking real steps to make design chain integration easier, allowing direct access to their "Open Access" and Milkyway databases. This will obviate the need to create data interchange formats such as text-based flat files, which Barcelona Design's Ariel Sella says can cause inadvertent addition or loss of information. Synopsys' Rich Goldman adds that increasing chip densities sometimes made such text-based files gigabytes in size, so that more time was required to read and write the file than spent actually using the tool. Gartner analyst Daya Nadamuni says the EDA industry lags other business software sectors, such as enterprise software, which have taken advantage of Internet-based protocols. Synopsys recently offered third-party EDA developers access to its Milkyway database through downloadable APIs, while Cadence is "going completely open source," according to Cadence's Charlie Huang. He says EDA tool developers are able to easily browse and query Cadence's "Open Access" database, which has been handed over to industry consortium Si2. Nadamuni says customer demand prompted the moves, but that Cadence and Synopsys will also be able to more easily integrate their own technology, since both companies have grown capabilities largely through acquisition.
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  • "Computers That Do Windows"
    Technology Review (09/03) Vol. 106, No. 7, P. 30; Huang, Gregory T.

    Japanese and U.S. research labs have separately created transparent transistors this year using oxide semiconductors together with other chemical layers on glass. Previously, oxide semiconductors have not had sufficient electrical properties to be used for applications other than windshield defrosters and conductive coatings in touch-screens. The improved electrical properties mean transparent electronics applications such as video advertisements on storefront windows, or drivers' warnings shown on a car windshield are now possible. Laptop displays could also be significantly brightened with the new technology, since current silicon transistors block much of the backlight in the screens. On-off speeds may improve enough to allow transparent processors in the future. Oregon State University electrical engineer John Wager says that, eventually, "anywhere there's glass, there can be electronics." Besides Oregon State, DuPont in Delaware, and Tohoku University and Tokyo Institute of Technology in Japan have fabricated transparent transistors.
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  • "How HOT Is That CHIP?"
    Desktop Engineering (09/03) Vol. 9, No. 1, P. 32; Liu, Bau-Min

    Thermal management issues in microprocessor design can cause time-consuming delays after the prototype has been built and tested, but these problems can be overcome by using special computational fluid dynamics (CFD) software to iron out wrinkles before physical testing. Advanced Micro Devices senior engineer Bau-Min Liu writes about his experience using such software to identify and fix thermal problems before building the prototype. CFD software even helps with predicting junction temperatures. Liu also says AMD's FLO/STRESS thermomechanical stress module uses geometry and temperatures created for CRD analysis to conduct the stress analysis.

  • "The Evolution of the Connector Design Cycle"
    Wireless Design & Development (09/03); Jones, Terry; Bergey, Dana

    Not long ago, connector designs were created after critical system design elements and depended mostly on mechanical requirements. Today, high-speed signal requirements make early connector design collaboration and modeling tools necessary for marketplace success, write Terry Jones and Dana Bergey of FCI Electronics. As soon as the design concept is developed, the signal integrity engineering group of the connector supplier needs to be brought in to model and test the design, if needed. Perhaps an existing connector product can be used, but if a totally new design or approach is required, then early-on collaboration will ensure electrical and mechanical design requirements are optimally fulfilled. By starting design collaboration early, manufacturability and cost issues can be factored in, shortening the development cycle. Early simulations allow teams to decide which trade-offs they are willing to make between electrical and mechanical performance goals.
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  • "Smart Sensing Power on a Chip"
    Sensors (09/03) Vol. 20, No. 9, P. 42; Sinha, Priyabrata

    The increasing complexity of sensor-based applications makes it vital to increase the amount of intelligence embedded in the sensor interface, and what is more, the physical dispersal of sensors within a system makes it attractive to try to offload some of this processing away from the central control unit and closer to the sensors themselves. Digital signal processors (DSPs) are often used for operations such as a finite impulse response, infinite impulse response, or fast Fourier transform, but DSPs by themselves do not make very good sensor interfaces for various reasons. One solution to this problem is the digital signal controller (DSC)--a system-on-a-chip architecture, such as the Microchip Technology dsPIC30F sensor processor, that combines a master controller's (MCU's) control features with a DSP's functionality. A true DSC will have two 40-bit accumulators, which can handle the data from a 16-bit by 16-bit multiplication and also allow for some temporary data overflow that a 32-bit accumulator would not have room for; meanwhile, a DSC's central processor can optionally use a mechanism called saturation to keep a value within a permitted range and can handle rounding or scaling of data. Other features are a flexible interrupt structure, runtime self-programming, in-circuit serial programming, a high-resolution ADC, high-speed input capture, input/output change notification, and a universal asynchronous receiver transmitter interface for various communication peripherals. Some typical sensor applications in which DSCs can be useful are temperature sensors, passive IR detection, gas sensors, glass-break detection, gyroscopes, engine knock detection, vibration sensors, tire pressure monitors, data loggers, and fingerprint recognition. The article's author is applications engineer at Microchip Technology's Digital Signal Controller Division.
    "24/7 Design Help: Just a Click Away"
    Electronic Design (09/15/03) Vol. 51, No. 20, P. 53; Maliniak, Lisa

    A number of convenient Web sites are available to offer information at any time to help engineers with design problems. Many of the most useful sites are those offered by vendors, such as Analog Devices (www.analog.com), Apex Microtechnology Corp. (www.apexmicrotech.com), and National Instruments Corp. (www.ni.com). Not only can useful information be found on these sites, but other functions such as online ordering of samples are available as well. National Semiconductor (www.national.com) is one of the vendor sites that offer product-independent resources, such as online seminars, a technical journal, and an "Analog University" in the site's "Explore" section. Similarly, Actel (www.actel.com) offers a resource center for ASIC and FPGA design engineers. Site designers make use of user opinions and feedback to help make their sites better, while other companies, such as Texas Instruments (www.ti.com), make use of focus groups. Also available online is peer-to-peer support, such as the discussion groups on both Texas Instruments' and National Instruments' sites, as well as self-service resources, such as the "Software College" on Intel's site (www.intel.com). Other sites that could be of use to design engineers include:

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