Despite critics predictions that structured ASICs were a fad, vendors say business for the offerings is taking off. There is also a formal industry association being formed with 90 percent of existing structured ASIC suppliers purportedly involved, along with some EDA firms. Hewlett-Packard Electronic Systems Technology Center manager of ASIC and ASSP technology, Mobashar Yazdani, says all of the existing solutions require just one-tenth of the non-recoverable engineering costs of a normal ASIC design, but he also warns "it's not as simple as it looks." As for per-unit price, structured ASICs are usually twice that of normal cell-based designs, but less than an FPGA, and are ideal for volumes between 10,000 units and 100,000 units, says Yazdani. LSI Logic RapidChip's Mark Nelson, whose company insists its platform approach is distinct from other structured ASIC offerings, says time-to-market and cost considerations are driving the in-between trend. A 12-million-gate design might have to be partitioned into two or three structured ASICs, he says, so that chip-level performance and system architecture is impacted slightly. Altera is moving toward the middle with its HardCopy technology, which it now says does not require an FPGA design to create a HardCopy ASIC. Xilinx, meanwhile, continues to resist the trend, saying that IP selection and placement issues force down tool prices and alienate EDA software partners. In-Stat/MDR analyst Jerry Worchel, while predicting a $460 million market for structured ASICs by 2007, also warns that current offerings are not differentiated enough to satisfy system designers.
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A handful of young Arab engineers have created an online open-source organization that seeks to give designers and engineers from the developing world an outlet for their creative talents. Site co-founder and Ramallah-based FPGA design engineer Jamil Khatib says Handasa Arabia, or "Arabic Engineering," will enable engineers from developing nations to keep up to date on the latest technology and to bridge educational, technological, and cultural gaps. Khatib has already set up www.OpenCores.org, a Web site offering open-source chip IP, and produced OpenTech, a $25 package containing open-source design automation tools and IP. He says open-source cores are easy to design because they require only simulation tools and a programmable logic prototype board for testing. The Handasa Arabia site lists the first Arabic PDA project, called OFOQ, which currently has an implemented and synthesized core processor, though three graduated versions of the Linux PDA are described in the project outline. Co-founder Mohamed Salem, a hardware design engineer in Cairo, Egypt, says Handasa Arabia already has participants in the United States, Canada, Europe, India, China, Indonesia, and Malaysia, and is also drawing interest from university graduate students. He believes corporate sponsors will accelerate the site development once real products are created.
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A new water-based pump system for cooling laptop and PCs uses no moving parts and can service chips radiating up to 120 watts of heat per square centimeter. The Intel Centrino chip radiates 35 watts per square centimeter. Designed by Stanford University mechanical engineer Ken Goodson, the unique pump is actually a disc of glass two millimeters thick and five centimeters in diameter, and has one-micron-wide tubes passing from top to bottom. By applying an electric charge to the disc surface, ions are drawn into a flow and drag water along with them. According to experiments, this electro-osmosis flow carries 200 milliliters per minute. Cooligy, the startup firm commercializing the technology, says fans cannot keep pace with the heat by-product of Moore's Law because faster fans are both more noisy and prone to mechanical failure. But Paul Lee of QuietPC, which specializes in reducing computer noise, says any design mixing electricity and water has to be suspect conceptually, and that fans will continue to be the least expensive option for at least five years.
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STMicroelectronics announced that it is signing on as a governing member of the working groups at the Open Core Protocol International Partnership (OCP-IP), a nonprofit industry organization seeking a common standard for IP core interfaces that facilitate plug-and-play system-on-chip (SoC) design. According to the group, OCP is not a rigid bus interface but is at a higher level of abstraction than that. A standard socket is expected to allow IP designers to make cores independent of particular bus protocols and design implementations, as well as allowing development of reusable IP and IP integration in complicated SoC designs. "We count on this to further evolve our system level designs and to reduce complex SoC product design cycles and time-to-market," says Aldo Cometti, ST Microelectronics director of development and OCP-IP GSC member. Other companies at the head of the organization are Nokia, Texas Instruments, United Microelectronics Corp., and Sonics.
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Carnegie Mellon professor Seth Goldstein says chemically assembled electronic nanotechnology (CAEN) will enable tremendous leaps in chip performance over the next 10 years and strip out much of the non-recoverable engineering costs of chip design. The idea still needs research, he says, but CAEN may be the most important semiconductor technology since the CMOS manufacturing technique. It will facilitate a new class of electronics utilizing chemical self-assembly rather than photolithography. With up to one billion molecular switches per square centimeter, a large mesh of wires and switches would be matched with a standard silicon-based die containing power, clock lines, I/O interface, and support logic. Each switch would able to hold its state once programmed and thus remove much of the overhead assumed with current ICs.
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The Power5 server chip that IBM plans to introduce next year will offer a multithreading function. Multithreading is an emerging technological concept that would have chips run two "threads" of the same application, or two applications, at the same time. Microprocessor designers are focusing more on multithreading and multicore chips because they are looking for ways to improve the performance of chips at a time when they are more concerned about energy consumption. Multithreading chips also reduce chip idleness but enabling various chip components such as the floating point unit to operate independently, thus boosting efficiency. Insight64 analyst Nathan Brookwood says, "Simultaneous threading is a good way to recover some of that lost time." The Power5 is about 24 percent larger than the Power4+, and the multithreading approach will boost its gross power consumption, but IBM officials expect chip performance will improve by more than one-third. During the recent Hot Chips semiconductor design conference at Stanford University, Joel Tendler, director of technology assessment in IBM's systems group, said, "We're seeing in the order of 40 percent [in performance improvement] being pretty common" in lab tests.
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This year's Hot Chips conference received updates on new supercomputing strategies, ranging from the vector processing NEC Earth Simulator in Japan to molecular-scale memories and programmable logic arrays under research. Cal Tech computer science assistant professor Andre DeHon described nanowire research that would create wires just six to eight atoms wide and at a 10nm pitch. He said molecular-scale devices built with this technology could come within five years. DeHon also spoke about a chemical vapor deposition process that produced nanowires 20 microns long, which are then doped and etched into programmable memory or logic arrays. Although not faster than CMOS, DeHon said these devices could run at 10 GHz speeds. Cray hardware architect Robert Alverson said his company's Red Storm supercomputer, to be completed for Sandia National Laboratories by the end of 2004, will utilize 10,368 AMD Opteron processors and a complex Seastar chip used for system functionality. Seastar has seven ports linked to a 3D mesh and 800 MHz DDR Hypertransport interconnect, allowing four Opterons, four ASICs, and a management controller be integrated on a single card. Alverson said Cray would use symmetric multiprocessing in future systems and Red Storm did not because of time-to-build constraints.
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Fewer companies today can afford to follow Moore's Law, creating a divide between the have's and have not's in the semiconductor industry. Mixed signal integration is falling out of favor as the 90nm process ramps us, and Analog Devices and National Semiconductor--the two largest makers of such devices--are trending toward multiple-chip packages or multiple packages. Because of power management tissues, older chip generations are becoming more attractive, especially when packaged together. And the design work necessary to utilize 100 million gates at 90nm promises to take as much as three years, according to one analysis, while time-to-market speeds up. National Semiconductor fellow Dennis Monticelli says the economic pressures of dealing with advanced technology has created a divergence among chip companies. Integrating everything on a chip has proven inefficient for most applications, he says. Analog Devices high-speed communications group director Dave Robertson says low signal-to-noise ratio that accompanies low voltage requires a new architecture and topology for mixed signal chips. Cypress Semiconductor CEO T.J. Rodgers compared Moore's Law to a train leaving from New York's Grand Central Station. As the train goes further, the ride becomes more expensive. He says 130nm was the last cheap development node, and that many companies will have to fall back in development. Chartered Semiconductor's Kevin Meyer says IDMs such as Intel and IBM stand to gain from faster to-market speeds since they have resources to integrate all components on a smaller chip. Cypress' Rodgers agrees small design firms cannot front the investment needed for today's state-of-the-art designs. He says, "The whole fabless model is a bug headed for the windshield of a car."
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The ACM/IEEE Design Automation Conference (DAC) has issued its call for technical papers, special topic sessions, panels, tutorials, and student design contest entries. The 41st annual DAC will take place in the San Diego Convention Center June 7-11, 2004. DAC design methods technical program co-chair Limor Fix says the number of paper submissions has steadily grown during the past several years and should result in an excellent technical program next year. The conference will feature a Design Methods Track, papers for which should focus on creative experiences and innovative methodologies. For the Design Tools Track, innovative algorithms resulting from recent research and development are needed. And for the Embedded Systems Track, both tools and methods should be covered in papers, on topics such as low-power, embedded software, hardware and software co-design, and hardware and software platform design. In addition, the Student Design Contest will accept operational and conceptual entries--the first having proof-of-implementation and the second requiring a complete simulation. Submissions for both categories must have been completed after June 2002 and part of the student's university regimen.
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Researchers in Texas are working to keep the state at the forefront of nanotechnology semiconductor application by devising ways to get electrons to flow smoothly down copper wires. As chip geometries get smaller, electron interference becomes more of a problem and requires better insulation. University of North Texas researcher Rick Reidy says his group's work is vital to the national economy, since economic growth is dependent on productivity gains resulting from chip improvements. If researchers are no longer able to reduce chip sizes, he warns of economic stagnation. The University of North Texas and Texas Instruments researchers jointly received $2.2 million from the National Science Foundation to pursue their work. Rice University nanotechnology guru Wade Adams explains the problem for chip researchers at the nano-level, "You can't just put an atom somewhere and expect it to stay there." Besides cross-talk, Texas researchers are looking at new ways to manipulate molecules, with some favoring mechanical force and others non-conventional methods like optical tools. Favoring what he calls "laser tweezers," University of Texas at Arlington associate professor J.C. Chiao also says smaller electronics will mean new forms of power can be employed, including body heat and solar energy. Texas Nanotech Initiative President James Von Her warns that Texas institutions need to continue investing in nanotechnology or else risk being left behind in the rapidly advancing sector. On a national level, he says the government should do more as well, citing Japan's $1 billion nanotechnology investment this year, compared to $800 million planned by the U.S. government.
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Japanese silicon manufacturing equipment firm Disco expects sales of its "dicing before grinding" (DBG) systems to increase significantly through 2008 as demand for ultra-thin chips increases. By dicing wafers into chip sections before grinding them, Disco says it can make chips just 0.05 mm thick without increasing breakage. Its super-precise grinding wheels can cut a human hair 80 micrometers wide into 15 slices of equal thickness. Currently, chips are usually made about 0.3 mm thick so they can withstand production activities such as lithography and cutting, but there is no need to make chips that thickness for reasons other than sturdiness. By dicing chips before grinding them, Disco can circumvent some of those requirements. Disco sells a complete production line of DBG systems to companies such as Infineon. Radio frequency identification tags are among the many applications that would benefit from much thinner chips.

Taiwan opened its Si-Soft Research Center for SoC design, including IP, SoC platforms, certification, testing, and research and development on July 31. The center already has three tenants and will eventually house 21 companies, including nine foreign businesses. Taiwanese Premier Yu Shyi-kun presided over the inauguration, and said the new center marked an important shift from Taiwan being No.1 in semiconductor manufacturing to No.1 in semiconductor design. Semiconductor manufacturing is Taiwan's most competitive industry, but rising revenues in the design industry make that sector a key goal for the government. The government has a goal to attract 80 percent of the world's design contracts to Taiwan. Along with the new Si-Soft Research Center in Hsinchu, there is also the IC design park in Nankang, Taipei, which is geared more for systems manufacturers. Taiwan is also planning a second design center for the U.S. West Coast that would promote Taiwanese design business.

Researchers have harnessed an atomic force microscope to etch quantum-scale electronic circuits directly on semiconductor material. The process is reversible, like an Etch-A-Sketch toy, making testing of quantum design effects much easier than with one-off conventional lithography test designs. MIT quantum semiconductor expert Ray Ashoori says the flexibility of the new erasable electrostatic lithography (EEL) technique makes it a very powerful tool for studying quantum design characteristics. Instead of using a polymer layer as a stencil for creating electrodes with light, EEL deposits spots of charge directly on the surface of the semiconductor. Underneath, a layer of electrical charge works to keep surface charges in place by careful placement and repulsion. Changing the atomic force microscope charge turns it into a sort of eraser, so users can adjust lines and dots. A red light shone on the entire surface works to erase all the work just as shaking an Etch-A-Sketch erases the entire slate. The technique, however, requires extremely cold temperatures to keep the surface electrons from sliding around, though the quantum observations taken at that temperature should be relevant to normal room temperature.
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Microsoft's Smart Personal Objects Technology (SPOT), reportedly a personal passion of Bill Gates, is set to hit the U.S. market by year's end in a number of wristwatches from Fossil, Citizen Watch, and Suunto. The microcontroller component of the watches' two-chip chipset was designed and implemented by National Semiconductor's Bangalore design center. National Semiconductor India Designs (NSID) managing director Ashok Kumar says the project was in the works for more than two years, but that NSID was able to complete the design in just four months, concurrently developing the silicon, driver software, and validation boards, and using some existing peripherals. The device required stringent security controls and a small size, but the most important factor was manufacturing cost-effectiveness at high volumes. The microcontroller will process signals gathered by the custom-designed FM radio chip. Microsoft's SPOT allows small devices to receive data via FM infrastructure, including news, sports, weather, and traffic information. Microsoft and National Semiconductor are partners in developing SPOT chipsets, and Kumar says the same microcontroller will likely be used in other SPOT devices, with some modifications.
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The National Institute of Standards and Technology (NIST) is working on ever-smaller measurements that will help the semiconductor industry research, design, and manufacture at the nanoscale. The measurements are based on atoms as they are in perfect crystal. NIST researchers have already built a scanning tunneling microscope device meant to write atomic-level patterns, and are improving their technology to be accurate to within one nanometer. Eventually, the semiconductor industry will have benchmark references necessary for research and production at those sizes. The NIST's "atom-based artifacts project" team has combined interferometer devices in a new device that can measure distances in tens of picometers, or increments less than one-hundredth of a nanometer long. Interferometers measure distances using light interference patterns. So far, line widths just 10 nm, or about 30 silicon atoms across, have been achieved with the measurement references.
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The author spoke with several EDA-industry players about the state of the EDA industry in Canada. Scott McClellan, president and CEO of Ontario-based Icinergy Software, explained how the EDA presence in Canada was created in part by the large CAD department that Nortel/BNR in Ottawa had in the 1980s. Among the EDA companies in Canada, he said, are ADA in Ottawa, Electronics Workbench in Toronto, and Quantic EMC in Winnipeg, as well as some development operations of Cadence. In addition, part of Synopsis has its roots in Canada: The company Cadabra, which was started in Ottawa, was later bought by Numerical Technologies, which in turn was bought by Synopsis. Another person the author spoke to was Grant Martin, a fellow at the Cadence Berkeley Labs in Berkeley, Calif., and a onetime employee of Nortel/BNR in Ottawa; he described the history of Nortel's CAD venture as well as prominent players who worked there and companies that spun out from it. Another Canadian designer is Canadian Microelectronics Corp.'s Peter Stokes, who stated that his company is "providing an environment that is disproportionately rich for innovation in EDA, semiconductors, and microelectronics," and that firms from places as far-flung as "Korea, Japan, Taiwan, and Australia are coming to visit and to learn about our formula [for success]." Next was Vinod Agarwal of LogicVision in San Jose, who formerly held an endowed chair at McGill University in Montreal, who pointed to federal and provincial tax incentives as well as the heavy concentration of universities in Canada as reasons for doing research and development work there. Finally, the author spoke with two representatives of Analog Design Automation, a company that originated in Ottawa but now has its headquarters in Silicon Valley.
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European researchers with the Smart-Its Project continue to make progress on "ubiquitous computing." During the recent computer graphics Siggraph exhibition in the United States, Smart-Its Project researcher Martin Strohbach explained that his colleagues at Lancaster University and other institutions in Zurich, Germany, Sweden, and Finland envision embedding all kinds of everyday household items with programmable microchip sensors, which would give them smarts. "For example, we have used a table as a mouse pointing interface so you can control the TV or computer," says Strohbach. Bookshelves that warn people when they are overloaded and water bottles that tell users when their contents need to be cooled are additional fun ideas for such technology, but ubiquitous computing could have more serious applications, and may even help save lives. Sensors placed in floors would be able to determine that an elderly person has fallen and is unable to stand up. And a medicine cabinet could be transformed into a unit that tracks its contents and guides people through taking medicine. DIY flatpack chips have been developed that sense movement and use a voice to warn people when they are making a mistake in assembling products.
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Most chip designers are optimizing their designs by working directly with the RTL code, continuing to partially negate the "automation" aspect of electronic design automation (EDA). SystemC promises a way to avoid hands-on tweaking and thus dramatically reduce design cycle times. Forte Design Systems technical marketing vice president Mike Meredith says timing closure, for example, can be achieved by recompiling the chip with his company's SystemC implementation. The designer can specify each chip block use a certain percentage of the clock cycle, thus promising a finished design with adequate timing closure. While such a design may not perform as well as with some experienced hands-on work, American Technology Research analyst Erach Desai says the performance cost would be offset by increased productivity. Productivity is vital to commercial success as chip technology advances, making design efficiency less important in many areas. In analogy, software developers had to be weaned from reprogramming subroutines in assembly language as commercial pressures forced on-time delivery and new uses of computing power. Synopsys marketing vice president Farhad Hayat, however, says most designers still prefer to work with familiar languages. Gartner chip analyst Gary Smith warns that some companies still relying heavily on RTL work may find themselves at a competitive disadvantage, especially with larger designs. Some designs will always require expert optimization, including chips with analog components, according to National Semiconductor engineering expert Robert Pease. Even Open SystemC Initiative chief strategy officer Guido Arnout admits performance-driven CPUs built by Intel and AMD will probably never be designed entirely by computer, but insists "if you're designing the next digital camera and you're still tweaking, you're probably doing the wrong thing."
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In order to get more efficient use of on-chip resources with an FPGA, it may be possible to eliminate the use of the control port, which would free up more gates and I/O pins for other uses. Designs for which this is possible are "quasistatic" designs--that is, designs where the control port is only active right after power-up for the purpose of setting system parameters in the FPGA. Most devices that use FPGAs never actually take advantage of the possibility of reprogramming the FPGA a virtually unlimited number of times, which means the necessary configuration time at each power-up could be considered more of a nuisance than anything. Simply making a collection of configuration files for each possible device setting would be one potential way of avoiding the control port, but this would be a very inefficient way of using embedded memory, so the best approach it is to determine the structure of the configuration file and the meaning of the contents, and then figure out how to alter the contents to change the design's behavior. The process of doing this would begin with the lookup tables (LUTs) on the FPGA die, whose contents undergo an initialization process at configuration time by using a user- or engineer-defined value that is retained by the configuration file. Making use of the LUTs essentially consists of transforming the new settings in a series of bit positions and bit values, then patching the original configuration file, which means the only information that would have to be filed is the location of the relevant LUT bits in the configuration stream. In some cases, the FPGA vendor will actually provide information about which LUT location corresponds to which bits in the configuration file; one vendor that is known to publish all this information is Xilinx. When this is not the case, however, the relationship between LUTs and bits can still be determined through analysis of some well-chosen designs, although it is best to ask the vendor's permission before doing this.
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By 2010 plastics could rival silicon as the basis of electronics for all except heavy-duty tasks. Ohio State University Center for Materials Research head Arthur J. Epstein expects conducting plastics to facilitate single-electron transistors which store data in the electron spin and are controlled by magnetism. These electronics could be printed using spray-on inkjet techniques, similar to a process used in 17-inch organic light-emitting diode (OLED) displays made this year by Toshiba and Matsushita. OLED displays, made from polymers, use less power than other technologies, which has implications for mobile computing. Hewlett-Packard Laboratories last year created transistors from benzene-and-hydrogen molecules, a breakthrough Morgenthaler Ventures partner and former AT&T Bell Labs researcher Greg E. Blonder says follows natural law. "Nature computes with molecules," he explains. Dow Chemical, Motorola, and Xerox are collaborating to create better plastic electronics printing methods that may lead to applications such as video wallpaper. DuPont, Universal Display, Sarnoff, and Lucent Technologies are doing similar work. "Wall-size displays are going to happen--perhaps within five years," says University of Texas electrical engineer Ananth Dodabalapur.
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Chip designers need to consider the power requirements of their high-performance IC devices when in an environment traditionally employing low-performance peripheral devices. But because of the complexities of designing power circuits, many designers simply opt for off-the-shelf solutions that can have a serious impact on performance and cost. Using a commercially available step-down (buck) converter IC as a reference, designers can create a power circuit that fits load response, frequency, power capability, and other specifications more closely. There are 10 general rules for designing these devices. First, power requirements should be calculated at the outset and used to choose the appropriate design type. A converter should be placed next to each high-power device, with a separate ground path that will lower noise disruption in analog circuitry. Other insights include input considerations, remembering Ohm's Law, and understanding the difference in capacitors.
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Experiments with quantum circuitry have thus far produced a few quantum-circuit elements via careful lithography, but this does not translate well to producing large circuits with many quantum devices, largely because miniscule changes in fabrication would produce substantial differences in device characteristics. One way forward with quantum circuitry, however, might be using scanning probe techniques. Already, scanning tunneling microscopes permit controlled placement of single atoms, and this technique is different from the technique used for creating ordinary semiconductor circuits today as well as most of the quantum circuit elements that exist. One group of researchers has had some success using the atomic force microscope (AFM) to create features on an insulating surface, starting with samples constructed from gallium arsenide wafers. Bias voltage applied to metal gates on the surface of the structures can enhance or deplete the electron density in a below-the-surface layer of material, essentially creating a two-dimensional "gas" of electrons. This is followed by scanning the metallic tip of an AFM just above the sample surface at a very low temperature; varying the voltage on the tip deposits electric charge onto the sample surface and repels electrons in the lower level, thus enabling the researchers to confine electrons in selected regions of the buried layer. This technique, called "erasable electrostatic lithography," is much faster than conventional lithography, although it does have some potential drawbacks. One potential problem is that the present technique only works at very low temperatures--not really a drawback at this point, given that the quantum components only function at very low temperatures--while another important limitation is that it requires serial drawing and tuning of each circuit element.
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New glues that adhere only to metals such as gold, silver, and copper could eliminate the use of solder in circuit boards, reducing assembly cost and environmentally harmful waste. University of Kent chemist Simon Holder recently presented his new glues to the Sixth International Conference in Materials Chemistry in Sheffield, England. While the glue molecules stick to certain metals by arranging in specific ways, they conform differently to other surfaces and can be washed off with water. A circuit board could be sprayed with the glue, the wires attached, silicon chips stamped in, and then the entire assembly could be washed with water. Holder said the washed-away glue could be dried and reused. The glue is also appealing for organic light-emitting diodes (OLEDs), which currently require several extra polymer layers to bond to gold electrodes. The glue would eliminate the need for extra layers. Holder said the glue is currently a semiconductor but he was confident of turning it into a conductor by adding iodine.

Motorola's DigitalDNA Laboratories has produced a test 4 MB memory chip that uses silicon nanocrystals to reliably store data. The success of the chip, part of a class called thin-film storage, is based on the nanocrystal spheres sandwiched between two oxide layers. The Motorola team was able to regularly create the spheres at the right size and density so that they prevent electrical charges from being exchanged. Conventional floating-gate non-volatile memory loses its entire charge because of a single oxide defect, but the new chip would be able to minimize defect effects. Also, the right density is required for data to be read reliably. The chip array was made from a 200 mm wafer at 90 nm. Motorola is refining technical specifications so the technology can be used in 2004 products, and is also working to further reduce die size.
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While the drive for reconfigurable computing has so far resulted in the failure of a number of businesses, such as Chameleon Systems, the idea remains attractive enough to be pulling in plenty of money from chipmakers. Among the startups that have raised millions in recent years include QuickSilver Technologies and Cradle Technologies. Ideally, reconfigurable chips would combine the best features of hardwired custom chips and the best features of programmable logic device chips. QuickSilver's reconfigurable chips are capable of being reprogrammed every few nanoseconds, essentially existing as libraries of preset hardware designs that can be transferred to the chip with each cycle, changing the chip from, say, processing global positioning satellite signals at one moment to processing cell-phone signals the next moment. Although QuickSilver and other firms have put more effort than they expected into bringing these chips to market, they are making some progress now. Two of QuickSilver's licensees are expected to complete chips this year--ChipsAG, which is working on chips for digital TV set-top boxes, and AOI Technology, a joint venture of QuickSilver and the camera company Olympus--while Cradle Technologies says it is close to customer launches in video-streaming applications. Other startups in the reconfigurable-chip field are Pact Informations Technologie, PicoChip Designs, Radioscape, and Mathstar, while big chipmakers are making deals as well: Motorola has invested in Morpho Technologies, Infineon Technologies has acquired Morphis Technology, Philips has acquired Systemonic, and Hewlett-Packard has invested in Synfora and Elixent.
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Laser technology is expected to provide a means of detecting killer defects in semiconductors that would otherwise become harder and harder to find as design nodes continue to shrink. For testing the chip itself, laser technology can be used for detecting subsurface errors and inspect high-aspect-ratio vias and thin-film diagnostics, while elsewhere on the production line laser technology can help qualify lens materials and inspect printed circuit boards' features. Inspection laser technology is often a generation behind lithographic technology, but for the most part the inspection wavelength does not need to be the same as the size of the killer defects themselves. One exception to this, however, is aerial image masking--for which accurate results can only be found at the exposure wavelengths--but this application does not necessarily use the same kind of lasers used on the production line itself. As the wavelength of the laser decreases, sensitivity increases, although adequate detection at a lower cost can be realized with a longer-wavelength laser by boosting the output power and illuminating the wafer at shallow angles; it is also important for inspection lasers to emit little noise. No matter the design node, inspection uses several different generations of laser technology, with ArF and KrF lasers usable for less critical layers while the most advanced functions are handled by the most advanced sources. At the 100-nm and 70-nm nodes, the sensitivity of scanning electron microscopy and extreme-UV instruments will be needed for patterned wafer inspection in the process research and development phase, but the throughput requirements are expected to sustain demand for scattering techniques, and in turn these will sustain demand for established laser technologies. Finally, laser suppliers will need to continue refining pump technology, cooling systems, and other elements in order to meet requirements for wavelength, power consumption, footprint, and other factors.
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